The present invention improves upon the industry standard Small Computer System Interface (SCSI), which is hereby incorporated by reference.
The SCSI interconnect was developed as a result of the proliferation of inexpensive VLSI device controllers which changed the economics of interfaces for small system storage devices. The inexpensive VLSI device controllers allowed a controller to be built in each device.
Also, because device interfaces are very specific to certain device types, many device level interface standards would have been required to service all small computer device types. As a result, having to connect every backplane bus to every device interface through a controller would require an almost unbounded number of specific controller products. The development of the SCSI standard allowed a single computer backplane slot to service a varity of devices.
In view of the above problems, a small system parallel bus was developed which generally met the small system requirements for a device-independent peripheral or system bus. The small computer system interface bus enjoyed significant market success and eventually became the industry standard SCSI.
The SCSI interface is a local input/output (I/O) bus that can be operated at data rates in excess of five megabytes per second depending upon the circuit implementation. The primary objective of the interface is to provide host computers with device independence within a class of devices. The interface protocol includes provisions for the connection of multiple initiators, i.e. devices capable of initiating an operation, and multiple targets, i.e. devices capable of responding to a request to perform an operation.
The SCSI architecture includes eight distinct bus phases: BUS FREE, ARBITRATION, SELECTION, RESELECTION, COMMAND, DATA, STATUS, and MESSAGE. The last four phases, COMMAND, DATA, STATUS and MESSAGE, are the information transfer phases as they are all used to transfer data or control information via the data bus. The SCSI standard provides Command/Data (C/D), Input/Output (I/O), and Message (MSG) signals to distinguish between the different information transfer phases. The target device drives the three signals and therefore controls all changes from one phase to another. Included within the Data phase and Message phases are the DATA IN, DATA OUT, and MSG IN, MSG OUT sub-phases respectively.
The SCSI standard places no restrictions on the sequences between the information transfer phases. As a result of not placing restrictions on the information phase transitions that can occur between phases during any transfer, i.e. Command Out, Data Out, Data In, Status, MSG Out, and MSG In, the number of interconnections which must be made are so numerous as to require software assistance for proper operation. A problem arises with software assistance in that it incurs software latency in servicing the changes in the bus conditions.
Further, the information transfer phases used in the SCSI bus require one or more request/acknowledge (REQ/ACK) handshakes between the initiator and target to control the information transfer. Each REQ/ACK handshake allows for the transfer of one byte of information. A synchronous data transfer using the SCSI bus must be previously agreed to by the initiator and target through an exchange of messages. The messages determine the use of the synchronous transfer mode by both SCSI devices and establish a REQ/ACK offset and a transfer period.
The REQ/ACK offset specifies the maximum number of REQ pulses that can be sent by the target in advance of the number of ACK pulses received from the initiator, thus establishing a pacing mechanism. The determination of the REQ/ACK offset in SCSI requires a negotiation between the target and initiator. A microprocessor is used to set up this value for each transfer. However, the negotiation of the REQ/ACK offset and the need to maintain the negotiated values can slow down the synchronous data transfer.
In order to check the integrity of the SCSI bus, the SCSI system uses byte parity as its sole mechanism for detecting data errors. The use of only a single error detecting mechanism presents problems for the proper validation of data.
Other known bus interconnects provide a fixed sequence of phase transitions, thus simplifying the protocol of the controller. Further, because some of these prior buses use a coaxial cable, the fixed sequences are so rigid that in the case of an error developing in one of the phases, the sequence must continue through the other phases before returning an invalid signal. Thus, if an error were to initially be detected in the command phase, the system must wait for the transitions through the data and status phases before returning an invalid or no acknowledgment (NAK) signal. This consumes more time and slows down the system.